The System/390 architecture is an evolution of the System/360, which was announced in April 1964. During this 34 year evolutionary process/, many new functions and instruction formats have been added; at the same time, compatibility has been maintained for most programs written for the original System/360. Many of the extensions are for complex functions in which an additional cycle or two during the instruction decode is not a significant performance problem.
There are however, certain cases in which a performance difference of one or two cycles can be very significant. In particular, the support for a new floating-point format requires more than 20 new instructions in the RX (register indexed from storage) format. There are not that many spare 1-byte operation codes in the RX format. Thus, we deem it necessary to provide an extended operation code for these new instructions. All previous extensions to add new instructions to the System/360 instruction set have been by means of an extended operation code of either four bits or eight bits in the next sequential byte of the instruction.
We note that for floating point the RS/6000 has a non-contiguous operation code within the 32-bit instruction format. The ESA/390 RI format also has a non-contiguous operation code, but within the first 16-bits of the instruction. How an extended operation code for new RX instructions can be done that provides support for high frequency operation needed a solution.